PIC18F45K80-I/ML【PDF 27/351 页】MCU PIC 32KB FLASH 44QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3861

23页 24页 25页 26页 [27页]28页 29页 30页 31页

PIC18F66K80 FAMILY

DS39977F-page 122

2010-2012 Microchip Technology Inc.

6.3.5

STATUS REGISTER

The STATUS register, shown in Register 6-2, contains

the arithmetic status of the ALU. The STATUS register

can be the operand for any instruction, as with any

other register. If the STATUS register is the destination

for an instruction that affects the Z, DC, C, OV or N bits,

the write to these five bits is disabled.

These bits are set or cleared according to the device

logic. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended. For example, CLRF STATUS will set the Z bit

but leave the other bits unchanged. The STATUS

It is recommended, therefore, that only BCF, BSF,

SWAPF

, MOVFF and MOVWF instructions be used to alter

the STATUS register because these instructions do not

affect the Z, C, DC, OV or N bits in the STATUS

For other instructions not affecting any Status bits, see

the instruction set summaries in Table 29-2 and

Table 29-3.

Note:

The C and DC bits operate, in subtraction,

as borrow and digit borrow bits, respectively.

REGISTER 6-2:

STATUS REGISTER

U-0

R/W-x

—

—N

DC(1)

C(2)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

Unimplemented:

Read as ‘0’

bit 4

Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative

(ALU MSB = 1).

= Result was negative

= Result was positive

bit 3

OV:

Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the seven-bit

magnitude which causes the sign bit (bit 7) to change state.

= Overflow occurred for signed arithmetic (in this arithmetic operation)

= No overflow occurred

bit 2

Zero bit

= The result of an arithmetic or logic operation is zero

= The result of an arithmetic or logic operation is not zero

bit 1

DC:

Digit Carry/Borrow bit(1)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

= A carry-out from the 4th low-order bit of the result occurred

= No carry-out from the 4th low-order bit of the result occurred

bit 0

Carry/Borrow bit(2)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

= A carry-out from the Most Significant bit of the result occurred

= No carry-out from the Most Significant bit of the result occurred

Note 1:

For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

operand.

For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

operand.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式